This means that the CPU SOC embeds an USB 3 line with PHY (physical converting unit). USB 3 is know to lead to 2.4 GHz interferences in some situations. Could it be the reason there are some/many 2.4 GHz issues with this product ? I hope the device can be physically powered off on the SOC and that this is actually done in Spark (if not and the USB 3 is not used internally, that would be nice to do so !)
from what i'm reading here : https://www.engadget.com/2016/04 ... ural-compute-stick/
i now believe that th eSpark is architectured in a similar way and the USB 3 link on the SOC is probably used internally inside the Spark.
I'd still like to know if those multi core chips onboard our Sparks are also running the FMS and critical functions (I would not consider this a safe design...)